What a surprising find! I would imagine Cortex-M3 (with 24 KiB RAM in total) a huge overkill for just power management. And it totally escapes me why the realtime co-processors are using a custom ISA solution rather than just using Cortex-M0/3/4. Would have been great to leverage the mature toolchain for Cortex-M!
Power management on modern SoCs is actually really complicated. There are dozens of power rails and clocks for different subsystems that all must be brought up and down with controlled order and timing if the device is going to work reliably. This kind of controller is routine on most "big" SoCs these days.
Presumably so they can share the workload with other tasks, like boot verification or low power sensor listening. The M3/M4 are still very small cores.
