ORCA – An implementation of RISC-V intended to target FPGAs (opens in new tab)

I've been wondering if one of those chips could fit a CPU.

How do you estimate this sort of stuff? I can estimate software decently, but the penalty for being wrong is seldom so bad. With a hardware project, things actually don't fit and you are out of luck.

Different FPGAs have different sorts of limits, not just 1 different number. Do you go by lines of Verilog/VHDL code? Do you go by some idea of "most crazy operation" and register width? How...?

I just started learning about opencores and various buses (wishbone, axi, etc.) I am surprised many designs say spartan 3 or some vendor specific Fpga. I thought an Fpga is an Fpga. Yet, I see logic analyzers, open source softcores, etc. target specific devices. What gives?

How is it different from PicoRV32? (https://github.com/cliffordwolf/picorv32)